1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection for integrated circuits, and in particular, to the use of a floating gate neuron MOS transistor for electrostatic discharge protection.
2. Description of the Related Art
With the down-scaling of CMOS transistors, the gate oxide may be as thin as 100 .ANG. or less. The high impedance node at the input may be easily charged by electrostatic charges to as high as 2000 V (of either positive or negative polarity) during handling. As a result, gate oxide on the discharge path of scaled down CMOS devices connected to the input node can be destroyed or damaged to cause subsequent failure early in the operating life of the device.
Input and output circuit terminals are designed with protection networks on the chip that provide a path for ESD and prevent the generation of excessive voltage across the gate oxide of the devices. One state-of-the-art gate protection network utilizes the parasitic SCR (Silicon Control Rectifier) device which can be fabricated using CMOS technology. In its "on" state, the SCR provides excellent protection for sensitive devices because its "on" resistance is low and the electrostatic charge can be quickly discharged with heat dissipation over a large volume. One way to trigger conventional SCR devices is using the current generated during "avalanch" breakdown of the n-well to p-substrate junction by applying sufficient voltage across the pnpn path in the SCR device.
However, some particularly sensitive devices may be damaged at voltages less than the SCR trigger voltage (V.sub.trig). Therefore, the SCR alone is useless for protecting these devices. For example, if V.sub.trig is around 30 V, the gate-oxide breakdown voltage and drain breakdown voltage of a MOS transistor in a 0.5 .mu. device (120 .ANG.gate oxide) are both less than 15 V. If the SCR is to provide protection against ESD at an input or output pad, then its V.sub.trig should be less than the drain breakdown voltage of the NMOS device at the output buffer or the gate-oxide breakdown voltage at the input pads.
A Low-Voltage Triggering SCR (LVTSCR) structure has been developed for ESD protection of submicron CMOS devices. These LVTSCR reportedly have trigger voltages that are lower than the gate-oxide breakdown voltage (the gate oxide breakdown field is .apprxeq.8.times.10.sup.6 V/cm) and the drain breakdown voltage of MOS transistors. As shown in FIG. 1, in a LVTSCR, an NMOS structure is incorporated into the SCR as a device for triggering SCR at low-voltage. In this structure, the drain device trigger voltage V.sub.trig is determined by the snap-back breakdown voltage of the incorporated NMOS device. The drain of the NMOS device is connected to the n-well of the pnpn path of the SCR device; the gate and the source are both tied to V.sub.ss. As a result, high voltage generated from the pad during an ESD event brings the NMOS device into snap-back breakdown at a lower voltage than the SCR structure. If the channel length of the MOS transistor in LVTSCR is smaller than 0.5 .mu., then the drain breakdown of the NMOS occurs at lower voltage; in turn, the SCR is triggered at lower voltage for the circuit. The equivalent circuits for two popular LVTSCR are shown in FIG. 1. In one LVTSCR, the pad is shorted to the n-well in the associated SCR path and has a higher trigger current; in the other LVTSCR, the pad is not shortened to the n-well. In the former, when the pad is zapped to high voltage, the snap-back current in the n-channel MOS initially forward biases the pnp bipolar device (Qp) and then the npn bipolar device (Qn), and finally the SCR path enters into latch-up mode. The positive ESD charge is then quickly removed through the SCR path without damaging internal circuits. The n-channel MOS serves the function of providing triggering current in order to trigger the SCR path into the "on" state. It is well known that the triggering current is larger when the n-well is shorted to the pad.
Similarly, a complementary LVTSCR structure incorporating a PMOS transistor is useful for protection against a negative ESD zap, as described by Ker, et al., "Complementary LVTSCR ESD Protection Circuit for Submicron CMOS VLSI/ULSI," IEEE Trans. Electron Devices, Vol. 43, No. 4, p. 588-598, 1996. When the pad is zapped to low voltage, the snap-back current in the p-channel MOS initially forward biases the npn bipolar (Qn) and then the pnp bipolar (Qp), and finally the SCR path enters into latch-up mode. The negative ESD charge is then quickly removed through the SCR path without damaging internal circuits. Again, the p-channel MOS serves the function of providing latch-up triggering current for the SCR path. The case when the n-well is shorted to V.sub.dd requires larger latch-up triggering current and hence requires a larger p-channel MOS transistor in the LVTSCR structure.
Several opportunities for improvements remain in conventional devices for ESD protection. First, since V.sub.trig is sensitive to process variations (such as channel length), it is desirable to enhance photolithographic technologies to print channel lengths of MOS transistors in LVTSCR structure that are smaller than the minimum feature size capability of the technique. Second, the snap-back breakdown voltage of the MOS transistors in LVTSCR varies with the channel length, and the effects of hot carrier generation during an ESD zap event. Third, it is desirable to be able to tune V.sub.trig without resort to changing the channel length of the MOS in LVTSCR devices. Finally, it is desirable to trigger the SCR device without the MOS transistor operating in breakdown.
Accordingly it is desirable to modify conventional MOS transistors in LVTSCR devices, so that V.sub.trig is controlled by the turn-on voltage of a floating gate MOS transistor by proper gate coupling to the floating-gate transistor.